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Key To Dependable And Optimised System Design


With modern-day complicated multi-chipset methods, energy supply designs have gotten difficult and extra important than ever. Energy integrity evaluation helps us perceive the influence of every part and its parasitic worth on the ultimate efficiency of the CPU and helps in designing an optimised system for dependable operation.

Energy distribution of a system performs an important position in its reliability and efficiency. Be it any system starting from cellphones to laptops to servers to nationwide grids which might be powering up the nation, key to dependable system operation is to ship correct amount of present to its totally different hundreds at proper voltage ranges.

Think about 0.7V DC voltage at CPU (central processing unit) energy enter that’s rated for 1-1.5V DC for steady operation or 350V AC at air-conditioner enter that’s rated for 230V AC. It’s a recognized reality what occurs subsequent. Both the CPU hangs on account of low voltage or the air-conditioner will get broken on account of excessive voltage at enter.

The query that arises subsequent is, how to make sure electrical reliability as a system designer? Energy integrity is the reply. Energy integrity ensures required voltage and currents are delivered from supply to load inside the system. Via energy integrity evaluation, one can perceive voltage ranges at varied system hundreds beneath worst-case working situations, which is the last word take a look at {of electrical} reliability. This text covers the ability integrity evaluation of digital merchandise solely.

Benefits for the designer

Energy integrity performs a big position within the success and failure of digital merchandise. Following are the important thing benefits of performing thorough energy integrity evaluation of a system:

  • Ensures design specs are met in any respect system stage elements throughout worst-case working situations.
  • Ensures the system is designed optimally, with proper stage of inbuilt security margins, making it cost-effective.
  • Stronger reliance on outcomes primarily based choices quite than expertise or thumb-rule primarily based design.
  • Permits system scalability and optimisations primarily based on particular person use circumstances. Needn’t depend on vendor pointers primarily based on generic designs that will not be cost-effective for a devoted software.

Energy supply networks modelling

All electrical merchandise, at fundamental stage, could be diminished to electrical networks for modelling objective. An influence supply community (PDN) includes majorly an influence supply, single or a number of hundreds, and an interconnect path between the supply and the load.

Fig. 1 reveals a simplistic electrical circuit equal of a PDN with load R related to voltage supply VS by way of path resistance RP. In an actual system, resembling a desktop or server motherboard, VS might be a voltage regulator (VR) powering up the CPU, which is modelled as R (load). The parasitic resistance of the format/path on board connecting VR and CPU is modelled as Rp. This easy PDN mannequin can be utilized to know the significance of energy integrity at preliminary levels of the design.

Basic electrical model of a power delivery network
Fig. 1: Primary electrical mannequin of an influence supply community

With rising CPU present, which can be attributable to improve in CPU clock frequency to execute a particular workload, voltage Vi at CPU enter reduces on account of larger voltage drop alongside the trail or resistor Rp. Each electrical half, resembling CPU, can have its most load demand Imax and minimal working voltage Vmin required for steady operation outlined within the half datasheet. Path resistance RP that ensures Vi >Vmin beneath all loading situations is termed as goal resistance (RGoal) of the design.

To mannequin the design parasitic extra precisely, sequence inductance of the format is taken into account as properly. With inductance concerned, it’s now not simply resistance however impedance Zp of the format that must be modelled. Structure Impedance Zp that ensures Vi >Vmin beneath all loading situations inside system frequency vary of operation is termed as goal impedance (ZGoal).

The primary goal of energy integrity evaluation is to make sure parasitic impedance Zp of a system is lower than ZGoal inside system frequency vary of operation. For any system, ZGoal might be decided primarily based on its most load demand and most peak-to-peak noise that may be tolerated at enter for dependable operation.

Fig. 2 reveals an influence supply community of a CPU on a server or desktop motherboard system. It consists of a VR module, which is the primary energy supply for CPU, adopted by bulk capacitors on the output of the VR for limiting switching noise or ripple. There are motherboard capacitors positioned near the CPU, that are largely multilayer ceramic capacitors (MLCC) that restrict voltage falls throughout sudden inrush present demand by CPU.

Power delivery network of a CPU on desktop or server motherboard
Fig. 2: Energy supply community of a CPU on desktop or server motherboard

The CPU could be related to the motherboard through socket mechanism or soldered down immediately throughout meeting course of. The printed circuit board that mounts the silicon die or CPU chip is named a bundle. On the bundle, there are land facet caps (LSC) which might be positioned within the pin subject area on the backside facet and die facet caps (DSC) which might be positioned proper subsequent to the silicon die.

Fig. 3 reveals an equal circuit mannequin of the ability supply community, together with sensible circuit fashions of every part, resembling capacitors. Energy integrity evaluation helps us perceive the influence of every part and its parasitic worth on the ultimate efficiency of the CPU and helps in designing an optimised system for dependable operation.

Equivalent circuit model of the power delivery network
Fig. 3: Equal circuit mannequin of the ability supply community

Energy integrity evaluation methodology

With understanding of the significance, lets talk about the method to be adopted for full PI evaluation of any given system. We begin with DC efficiency examine of the system adopted with AC or frequency area evaluation (FDA). On the finish, we should carry out the transient evaluation that gives closing go or no-go path for the design and is the last word take a look at for system reliability.

DC efficiency evaluation

DC efficiency is #1 precedence for any PDN. With DC evaluation, we guarantee design accounts for the next features:

  • Regular state voltage drop at totally different system stage elements from respective voltage supply.
  • Present densities alongside the format and its uniform distribution all through.
  • Most present flowing by way of particular person vias on PCB.
  • Energy loss contribution of every particular person board layer in case of multilayer PCB stack up.

Simulation setups for operating DC evaluation are quick and correct. DC evaluation is step one earlier than doing any type of frequency area or time area evaluation of the PDN.

Fig. 4 highlights a typical failure case of PDN that may be analysed and glued by way of DC evaluation. It reveals an influence format (highlighted in inexperienced) from VR output to the load level. At load level, the voltage drops from 1V to 0.74V, which can render the chip non-functional. With such gaps recognized, the format could be optimised to cut back voltage drops and meet design specs for all system stage elements by guaranteeing path resistance is lower than goal resistance RGoal.

PDN failure case with large voltage drop at load input
Fig. 4: PDN failure case with massive voltage drop at load enter

Fig. 5 highlights one other failure case of a PDN with ~6.5A present flowing by way of single through within the design. Typical specification for the standard PCB design is most 2A present although through. If not accounted for, such excessive present would result in through burn on PCB. Such points could be fastened by both including extra vias within the areas with excessive present densities or altering through location/sample within the format.

Fig. 5: PDN failure case with excessive present by way of particular person through

Frequency area evaluation

Frequency area evaluation is useful to know PDN efficiency throughout a spread of operational frequencies. With FDA, PDN impedance Z as a operate of frequency is plotted and in contrast towards goal impedance ZGoal to make sure Z<ZGoal for system vary of operational frequencies.

Additionally it is useful to know energy supply efficiency sensitivity with totally different kind of capacitors, resembling bulk caps, motherboard caps, land facet capacitor, and many others (as proven in Fig. 2), variety of capacitors and their respective placements. With optimum kind, mixture, and site of the capacitors studied and labored out by way of FDA, we will optimise and design an economical energy supply resolution, which is predicated on precise evaluation of the system and never simply thumb guidelines or generic vendor pointers.

Impedance as a function of frequency for a typical PDN network
Fig. 6: Impedance as a operate of frequency for a typical PDN community

Fig. 6 shows an impedance profile of a typical PDN. The assorted crests and troughs within the impedance profile are results of resonance and anti-resonance between varied sequence and parallel resistor-inductor-capacitor (RLC) combos, as proven in Fig. 3. Close to PDN proven in Fig. 3, the fixed/flat impedance area in low frequency vary of the profile is ruled by efficient resistance between the silicon die and VR supply.

The primary crest within the profile, round 100kHz frequency vary, is dictated by parasitic inductance of the majority capacitor. That is additionally known as third droop impedance. The trough near 1MHz frequency vary is ruled by the majority capacitor and different motherboard capacitors’ efficient capacitance.

The second crest level within the plot is dictated by the motherboard parasitic inductance and the CPU-motherboard interconnect parasitic inductance. This level is known as second droop impedance. The trough following the second droop is ruled by LSCs and the DSCs (die facet caps).

The steep rise within the impedance resulting in the third crest is dictated by bundle parasitic inductance and LSC/DSC parasitic inductance and is known as first droop impedance. The falling impedance in excessive frequency area >100MHz is ruled by metal-insulated-metal (MIM) capacitances contained in the silicon die.

It turns into extraordinarily vital to generate and perceive the impedance profile of the system beneath take a look at to run any type of optimisation on the identical. For instance, addition or elimination of bulk capacitor on motherboard is not going to have any influence on second droop impedance because it’s past the vary of its frequency response. Bundle capacitors and bundle format must be optimised for decreasing the identical. Such design stage understanding can solely be achieved by way of system frequency area evaluation.

Transient evaluation

Transient evaluation is the last word take a look at for system reliability. It helps in evaluating the ‘closing’ PDN efficiency with system stage specs outlined within the datasheets. Additionally, the outcomes generated could be correlated with precise validation outcomes to estimate the general simulation course of accuracy. It includes producing a time-domain passive circuit mannequin of the PDN beneath evaluation.

With circuit mannequin generated, correct voltage supply (at VR location) and sink hundreds (at load gadgets) could be related at respective nodes of the mannequin to generate an total circuit file. This circuit file could be simulated and analysed for outcomes utilizing any SPICE primarily based circuit simulator, resembling HSPICE, LTSPICE, and many others. The important thing outcomes generated are the time area voltage profiles on the enter of system stage part beneath take a look at, which then could be in contrast with the outlined specs.

Most vital a part of this course of is producing an correct circuit mannequin of the PDN community. Any device is nearly as good as its enter. On this case, SPICE simulator output outcomes are as correct because the circuit mannequin used to generate the identical.

Circuit mannequin technology of the PDN beneath take a look at is a two-way course of. At first, frequency area or s-parameter mannequin of the PDN community is generated utilizing 3D Finite Aspect Methodology primarily based solvers. As soon as the s-parameter mannequin is generated and verified for passivity and casualty, a circuit mannequin could be generated from s-parameter mannequin by way of macro-modelling primarily based software program instruments.

Time domain voltage profile across system device under test with load profile
Fig. 7: Time area voltage profile throughout system system beneath take a look at with load profile

Fig. 7 shows an instance of time area voltage and present profiles for any PDN beneath evaluation. A chunk-wise linear present supply related at load terminal is used as a stimulus to excite the PDN. Right here, the stimuli present rises from 17A to 37A in 1µs. In actual work software, any such load demand could be attributed to CPU working in turbo mode of operation, that’s, rising its working frequency to execute the workload.

With rise in present demand of the load, voltage at it enter drops to a minimal stage, ruled by PDN impedance Z, and rises again to the steady-state stage ruled by its DC resistance. At about 10µs, the present demand falls all of the sudden, which might be attributed to finish of workload execution and CPU decreasing its frequency of operation. On account of sudden lower within the load demand, voltage on the gadgets overshoots and hits a most worth earlier than settling again to the regular state.

The primary goal of the whole train of energy integrity evaluation is to make sure minimal and most voltage ranges at system enter measured in simulation are inside system working vary for dependable efficiency, and the simulation setup and outcomes match carefully with precise testing situations and outcomes.

Fig. 8 reveals system energy integrity evaluation workflow. It begins with sanity examine of system receivables adopted by DC efficiency examine. With DC criterion met, evaluation circulation strikes to frequency area evaluation. In frequency area evaluation, impedance profile Z of the system is in contrast towards ZGoal. If Z<ZGoal for system vary of frequency operation, the evaluation strikes to the ultimate stage of transient examine or time area evaluation.

Power integrity analysis workflow
Fig. 8: Energy integrity evaluation workflow

For time area evaluation, PDN circuit mannequin is generated first adopted by SPICE deck constructing. As soon as the computed voltage droop and overshoot meets the design specs, the ability integrity evaluation is concluded with excessive confidence design readiness.

Conclusion

With modern-day complicated multi-chipset methods, energy supply designs have gotten difficult and extra important than ever. Plenty of root-cause failures in defective methods could be one way or the other associated to the ability supply. With energy integrity evaluation workflow, this course of could be simplified. If it sounds too good to be true, let’s make clear that it does quantity to appreciable work and funding through the design part of the product. Nonetheless, it ensures clean design validation, dependable product efficiency, and higher buyer expertise, which on the finish interprets to higher gross sales and earnings, that are the last word objectives for any organisation.


Ashish Sharma is from Intel Know-how India Pvt Ltd, Knowledge Middle Energy Options, Bengaluru and Jagan Kandi is from Intel Company, Knowledge Middle Energy Options, Chandler, USA. They want to acknowledge Datacentre Engineering Group, Intel Company for sharing very important data and Fig. 2 by way of Fig. 6 that helped formulating this text.

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